Verilog HDL Codes

Half Adder Implementation using Verilog HDL

i)   Verilog HDL stands for Hardware Description Language.

                a. Switch Level

                b. Gate Level

                c. Data Flow Level

                d. Behaviour Level     ( most abstract )

Software tool that will be used to test functions is Model Sim.

How to Program?

i)  First of All, make module similar to function in other language such as C.

ii) Mention the inputs and outputs of the Module (like function/method C++).

iii) To test , make a test module.

                In test module , use a key word ‘reg’ before inputs and ‘wire’ before outputs.

                A simple Half Adder is given below.

Half Adder in Verilog;

module     ha (S,C,a,b)

input      a,b

output          S,C

XOR        #1(S,a,b)

and        #1(C,a,b)

endmodule

module     tbench_ha;

reg        a,b ;

wire       S,C ;

ha        f1(S,C,a,b)

initial

     begin

#5 a=1’b0 ; b=1’b0 ;

#5 a=1’b0 ; b=1’b1 ;

#5 a=1’b1 ; b=1’b1 ;

     end

endmodule